library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity assignment is
    port(
        enable: in std_logic;
        reset: in std_logic;
        a: out std_logic_vector(3 downto 0);
		 exhausted: out std_logic
    );
end assignment;
architecture assignment_behavior of assignment is
signal internal_assignment : std_logic_vector(3 downto 0) := "0000";
signal exhaust_temp : std_logic := '0';

begin
process(enable, reset)
begin
    if enable ='1' and reset='0' then

            internal_assignment <= internal_assignment + 1;
            if internal_assignment = "1111" then
                exhaust_temp <= '1';
            end if;
			
    elsif reset='1' then
        internal_assignment <= "0000";
        exhaust_temp <= '0';
    end if;
end process;
a <= internal_assignment;
exhausted <= exhaust_temp;
end architecture assignment_behavior;